所属分类：
其他
开发工具：Verilog
文件大小：9776KB
下载次数：13
上传日期：2017-07-30 21:30:31
说明： FPGA使用ADC0832来进行AD转换获得结果
(The FPGA to control ADC0832 to ADC)
文件列表：
TEST
TEST\AD.v
TEST\ADDA.asm.rpt
TEST\ADDA.bdf
TEST\ADDA.cdf
TEST\ADDA.done
TEST\ADDA.fit.rpt
TEST\ADDA.fit.smsg
TEST\ADDA.fit.summary
TEST\ADDA.flow.rpt
TEST\ADDA.jdi
TEST\ADDA.map.rpt
TEST\ADDA.map.summary
TEST\ADDA.pin
TEST\ADDA.pof
TEST\ADDA.qpf
TEST\ADDA.qsf
TEST\ADDA.qws
TEST\ADDA.restore.rpt
TEST\ADDA.sof
TEST\ADDA.sta.rpt
TEST\ADDA.sta.summary
TEST\ADDA.tan.rpt
TEST\ADDA.tan.summary
TEST\ADDA.tis_db_list.ddb
TEST\ADDA_assignment_defaults.qdf
TEST\AX301.tcl
TEST\bin
TEST\bin\assignment_defaults.qdf
TEST\DA.v
TEST\db
TEST\DB4CE15_ADDA .tcl
TEST\db\ADDA.ace_cmp.bpm
TEST\db\ADDA.ace_cmp.cdb
TEST\db\ADDA.ace_cmp.hdb
TEST\db\ADDA.amm.cdb
TEST\db\ADDA.asm.qmsg
TEST\db\ADDA.asm.rdb
TEST\db\ADDA.asm_labs.ddb
TEST\db\ADDA.cbx.xml
TEST\db\ADDA.cmp.bpm
TEST\db\ADDA.cmp.cdb
TEST\db\ADDA.cmp.hdb
TEST\db\ADDA.cmp.kpt
TEST\db\ADDA.cmp.logdb
TEST\db\ADDA.cmp.rdb
TEST\db\ADDA.cmp_merge.kpt
TEST\db\ADDA.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
TEST\db\ADDA.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
TEST\db\ADDA.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
TEST\db\ADDA.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
TEST\db\ADDA.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
TEST\db\ADDA.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
TEST\db\ADDA.db_info
TEST\db\ADDA.eco.cdb
TEST\db\ADDA.fit.qmsg
TEST\db\ADDA.hier_info
TEST\db\ADDA.hif
TEST\db\ADDA.idb.cdb
TEST\db\ADDA.lpc.html
TEST\db\ADDA.lpc.rdb
TEST\db\ADDA.lpc.txt
TEST\db\ADDA.map.bpm
TEST\db\ADDA.map.cdb
TEST\db\ADDA.map.hdb
TEST\db\ADDA.map.kpt
TEST\db\ADDA.map.logdb
TEST\db\ADDA.map.qmsg
TEST\db\ADDA.map_bb.cdb
TEST\db\ADDA.map_bb.hdb
TEST\db\ADDA.map_bb.logdb
TEST\db\ADDA.pre_map.cdb
TEST\db\ADDA.pre_map.hdb
TEST\db\ADDA.rtlv.hdb
TEST\db\ADDA.rtlv_sg.cdb
TEST\db\ADDA.rtlv_sg_swap.cdb
TEST\db\ADDA.sgdiff.cdb
TEST\db\ADDA.sgdiff.hdb
TEST\db\ADDA.sld_design_entry.sci
TEST\db\ADDA.sld_design_entry_dsc.sci
TEST\db\ADDA.smart_action.txt
TEST\db\ADDA.sta.qmsg
TEST\db\ADDA.sta.rdb
TEST\db\ADDA.sta_cmp.8_slow_1200mv_85c.tdb
TEST\db\ADDA.syn_hier_info
TEST\db\ADDA.tiscmp.fastest_slow_1200mv_0c.ddb
TEST\db\ADDA.tiscmp.fastest_slow_1200mv_85c.ddb
TEST\db\ADDA.tiscmp.fast_1200mv_0c.ddb
TEST\db\ADDA.tiscmp.slow_1200mv_0c.ddb
TEST\db\ADDA.tiscmp.slow_1200mv_85c.ddb
TEST\db\ADDA.tis_db_list.ddb
TEST\db\ADDA_global_asgn_op.abo
TEST\db\altsyncram_0eq1.tdf
TEST\db\altsyncram_6371.tdf
TEST\db\altsyncram_abq1.tdf
TEST\db\altsyncram_au14.tdf
TEST\db\altsyncram_gr81.tdf
TEST\db\altsyncram_k4p3.tdf
TEST\db\altsyncram_kr14.tdf
TEST\db\altsyncram_u1p3.tdf
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